Soitec Introduces 200 mm SmartSiC Engineered Substrate for Automotive Applications

Soitec Introduces 200 mm SmartSiC Engineered Substrate for Automotive Applications

Soitec, an industry leader in designing and manufacturing innovative semiconductor materials, has released its first 200 mm silicon carbide SmartSiC wafer. With the release, Soitec can enlarge its SiC product portfolio beyond 150 mm, take the development of its SmartSiC wafers to the next level, and cater to the growing demand of the automotive market.

The SmartSiC substrate in 200 mm emerged from Soitec’s pilot line at its Substrate Innovation Center within CEA-Leti in Grenoble. The release enabled Soitec to demonstrate the quality and performance of a 200 mm SmartSiC wafer and conduct the first round of key customer validations.

Soitec launched the construction of a new fab in France, Bernin 4, in March 2022. It is primarily dedicated to the manufacturing of SmartSiC wafers in 150 mm and 200 mm and is expected to be operational by the second half of 2023.

Soitec’s unique SmartSiC technology allows significantly enhances the performance of power electronics devices and boosts electric vehicles’ energy efficiency. The technology consists in bonding a very thin layer of high-quality SiC to a very low resistivity polySiC wafer.

Soitec’s SmartSiC substrates will be key for energy-efficient electromobility,” says Christophe Maleville, Chief Technology Officer of Soitec. “Our unique technology allows us to pioneer cutting-edge engineered substrates and open up new perspectives for power electronics in the automotive and industrials markets. The addition of 200 mm to our SiC substrate family allows us to further differentiate our portfolio and address an even larger variety of customer requirements, in terms of product quality, reliability, volume, and energy efficiency. The release of a 200 mm SmartSiC wafer is an important milestone in the development and deployment of our SmartSiC technology. It underpins our technological leadership, our capability to drive innovation and launch next-generation wafer technologies.”